Block diagram of 8086 microprocessor

Hello guys in this video we will see the functions of each pin of the 8086 Microprocessor,with the help if Block diagram of Microprocessor 8086. Microprocessor 8086 is very much important to study. so read this post properly. 

BLOCK DIAGRAM OF  MICRO-PROCESSOR 8086 

AD0 - AD15 : 

1. This lines are time-multiplexed bi-directional address and data bus.
2. During T1 clock cycle of the bus cycle, they carry lower order 16-bit address.
3. During T2,T3 and T4 they carry 16-bit data.

A19/S6, A18/S5,A17/S4,A16/S3 :

1. These are time-multiplexed address and status line.
2. During T1 clock cycle, these lines carry upper 4-bit address.
3. During T2,T3 and T4 clock signal S3 and S4 carry status signals and these status lines are used to identify memory segment

               

S4	S3	Segment Register
0	0	ES
0	1	SS
1	0	CS or NONE
1	1	DS

BHE'/S7  [ Bus High Enable / Status] :

1.  The BHE is a active low signal .
2. BHE indicate the transfer of data over higher order data bus.
3. The BHE'/S7 is time-multiplexed line, so during T2 to T4 the status signal S7 is transmitted on these line.

RD' [Read Output] :

It is an active low read signal issued by the processor to indicate that the processor is performing read operation with memory or I/O depending on the status M/IO' signal. 

READY  :

1. It is an active high input signal.
2. When high ,it indicates that the peripheral device is ready to transfer data.

RESET :

1. It is a system reset.
2. When this signal goes high , processor enter into reset state and terminate the current activity and start execution from FFFF0H

INTR  :

   This is a level triggered interrupt request input and is checked during the last clock cycle of each instruction to determine the availability of the request.

NMI  : [ NON-MASKABLE INTERUPT]

1. This is an edge triggered input interrupt request which causes a type-2 interrupt.
2. This NMI is not maskble by software means interrupt signal to this line cannot be avoided.

TEST' :

If this signal goes low, execution will continue else the processor remains in an active state.

CLK :

This clock input provides the basic timing for processor operation and bus control activity.

MN/MX' :

1. This pin indicates the operating mode of 8086.
2. When this pin is connected to VCC, the processor operates in minimum mode and when this pin is connected to ground, processor operates in maximum mode. 

 
INTA' :

1.  It is an active low output signal.
2. when processor receive INTR signal, the processor complete current machine cycle and acknowledge the interrupt by generating this signal.

ALE' : [Address Latch Enable]

It is active low signal issued by the processor during middle of T2 until the middle of T4 to indicate the availability of valid data over AD0- AD15

DT/R' :[ Data Transfer / Receive] 

When the processor sends data out, this signal is high and when processor receives data, then this signal is low.

M/IO' : [Status Signal]

when this signal is high, memory is accessed and when this signal is low, an I/O device is accessed.

WR' :[Write]

It is an active low signal issued  by the processor to write data to memory or I/O device depending on the status of M/IO'  signal.

HLDA : [HOLD ACKNOWLEDGE]

This is an active high output signal generated by the processor after receiving the HOLD signal.

HOLD :

1. When another master device needs the use of address,data and control bus, it sends a HOLD request to the processor through this line.
2. It is an high input signal.

QS1 , QS2  : [Queue Status ]

1. These lines provide information about the status of instruction queue during the clock cycle after which the queue operation is performed.

QS1	QS0	Status
0	0	No operation
0	1	1st byte of op-code from queue
1	0	Empty queue
1	1	Subsequent byte from queue

      2. These status signals reflect type of operation, being carried out by the processor and required by the bus controller Intel 8288 to generate all memory or I/O access control signals.

LOCK' : 

This output signal indicates that other system bus master will be prevented from gaining the system bus, while this signal is active low signal.

RQ'/GT0'  ,  RQ'/GT1': [Request/ Grant]

These pins are used by other local bus master in maximum mode to force the processor to release the local bus at the end of the processors current bus cycle.





That's all about the block diagram of microprocessor 8086 .....

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